1. Field of the Invention
This present invention relates to a liquid crystal display, and more particularly to a gate driving apparatus and method for a liquid crystal display panel that is adaptive for reducing the number of external driving integrated circuits connected to the liquid crystal display panel.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal having a dielectric anisotropy using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having a pixel matrix, and a driving circuit for driving the liquid crystal display panel.
Specifically, as shown in FIG. 1, the LCD includes a liquid crystal display panel 2 having a pixel matrix, a gate driver 4 for driving gate lines GL1 to GLn of the liquid crystal display panel 2, a data driver 6 for driving data lines DL1 to DLm of the liquid crystal display panel 2, and a timing controller 8 for controlling driving timings of the gate driver 4 and the data driver 6.
The liquid crystal display panel 2 includes a pixel matrix consisting of pixels formed for each area defined by the crossing of the gate lines GL and the data lines DL. Each of the pixels includes a liquid crystal cell Clc for controlling light transmission through the pixel according to a pixel signal, and a thin film transistor TFT for driving the liquid crystal cell Clc.
The thin film transistor TFT is turned on when a scanning signal, that is, a gate high voltage VGH from the gate line GL is applied, to thereby pass a pixel signal from the data line DL to the liquid crystal cell Clc. Further, the thin film transistor TFT is turned off when a gate low voltage VGL from the gate line GL is applied, to thereby keep the pixel signal charged in the liquid crystal cell Clc.
The liquid crystal cell Clc acts like a capacitor, and consists of a common electrode separated from a pixel electrode connected to the thin film transistor TFT having a liquid crystal therebetween. The liquid crystal cell Clc further includes a storage capacitor (not shown) so as to stably maintain the charged pixel signal on the pixel until the next pixel signal is charged. The liquid crystal cell Clc changes an alignment state of the liquid crystal having a dielectric anisotropy according to the pixel signal provided through the thin film transistor TFT to control light transmittance through the liquid crystal cell Clc, thereby implementing a gray level scale.
The gate driver 4 shifts a gate start pulse GSP from the timing controller 8 in response to a gate shift clock GSC to thereby sequentially apply a scanning pulse with the gate high voltage VGH to the gate lines GL1 to GLm. The gate driver 4 applies a gate low voltage VGL to the gate lines GL during the remaining intervals in which a scanning pulse with the gate high voltage VGH is not applied. Such a gate driver 4 includes a plurality of gate driving integrated circuits (IC's) as shown in FIG. 2 for the purpose of sharing the driving of the gate lines GL1 to GLn.
The data driver 6 shifts a source start pulse SSP from the timing controller 8 in response to a source shift clock SSC to generate a sampling signal. Further, the data driver 6 latches pixel data RGB input according to the source shift clock SSC in response to the sampling signal and then applies the latched sampling signal line by line in response to a source output enable signal SOE. Next, the data driver 6 converts the pixel data RGB applied line by line into analog pixel signals using different gamma voltages and applies them to the data lines DL1 to DLm. Herein, the data driver 6 determines a polarity of the pixel signal in response to a polarity control signal POL from the timing controller 8 when the pixel data are converted into the pixel signals. Such a data driver 6 includes a plurality of data driving integrated circuits (IC's) for the purpose of driving of the data lines DL1 to DLm.
The timing controller 8 generates a gate start pulse GSP, a gate output enable GOE, and a gate shift clock GSC for controlling the gate driver 4 and a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE and a polarity control signal POL for controlling the data driver 6. In this case, the timing controller 8 generates control signals such as GSP, GSC, GOE, SSP, SSC, SOE and POL using a data enable signal DE to indicate an effective data interval input from the exterior, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, and a dot clock DCLK to determine the transmission timing of the pixel data RGB.
FIG. 2 shows a plurality of (e.g., four) gate driving IC's 12 included in the gate driver 4 shown in FIG. 1, and FIG. 3 shows input/output waveforms of the gate driving IC's shown in FIG. 2.
Each of the gate driving IC's 12 shown in FIG. 2 is comprised of a shift register for shifting an input start pulse to generate a scanning pulse SP, and a level shifter array having level shifters to level-shift the scanning pulse SP from the shift register and to apply it to the gate line. In this case, a start pulse input into the first gate driving IC 12 is the gate start pulse GSP from the timing controller 8 while start pulses input to the remaining gate driving IC's 12 are carry signals CR1, CR2 and CR3 output from the pre-stage gate driving IC 12. Further, each of the gate driving IC's 12 is commonly supplied with the gate shift clock GSC including a plurality of clocks.
First, the first gate driving IC 12 shifts the gate start pulse GSP in response to the gate shift clock GSC to thereby sequentially apply the scanning pulse SP to the gate lines GL1 to GL(n/4). Then, the first gate driving IC 12 outputs the scanning pulse SP to the last gate line GL(n/4) and, at the same time, applies the carry signal CR1 to the next-stage gate driving IC 12.
The remaining gate driving IC's 12 shifts the carry signals CR1, CR2 and CR3 inputted from the previous gate driving IC 12 in response to the gate shift clock GSC to thereby sequentially apply the scanning signal SP to the gate lines GL(n/4)+1 to GLn as shown in FIG. 3.
The plurality of gate driving IC's 12 is usually mounted on a tape carrier package (TCP) (not shown) that is connected to the liquid crystal display panel 2. In this case, the TCP mounted with the gate driving IC's is attached onto the liquid crystal display panel 2 by a tape automated bonding (TAB) process.
The conventional LCD requires a plurality of gate driving IC's 12 for driving the gate lines GL1 to GLn. Therefore, the number of gate driving IC's 12 and the TCP's must be increased as the number of the gate lines GL1 to GLn is increased in accordance with the resolution, thereby causing a rise in the manufacturing cost.